Dynamic random access memories (“DRAMs”) are the most commonly manufactured product of all semiconductor integrated circuits (“ICs”). DRAMs are data storage devices that store data as a charge on a storage capacitor. A DRAM typically includes an array of memory cells. Each memory cell includes a storage capacitor and a transistor for transferring charges to and from the storage capacitor. Each memory cell is addressed by a word line (“WL”) and accessed by a bit line (“BL”) pair. The WL controls the transistor such that the transistor couples the storage capacitor to and decouples the storage capacitor from the BL pair for writing data to and reading data from the memory cell. Multiple word lines correspond to multiple rows of memory cells, while multiple bit line pairs correspond to multiple columns of memory cells.
DRAM array devices should be designed with minimum leakage currents so as to be capable of supporting as high as possible retention times. Therefore, the substrate voltage is conventionally connected to negative voltage levels, such as −0.5 V, to reduce leakage currents. However, this can result in increased source to substrate voltages, thereby increasing the threshold voltage and reducing device performance (e.g., reduced write back current). Additionally, DRAM devices may not share a common substrate, but may have individual substrate wells. Examples of such DRAM devices include silicon on insulator (“SOI”) DRAMs and vertical (e.g., trench technology) DRAM devices with complete body pinch off due to the buried strap (“BS”) beyond the cell dimensions. The BS provides the outdiffusion from the trench to the drain of the array device, thereby providing connection. Since the BS diffuses horizontally, it can eventually connect to the next trench, isolating the well.
It is therefore desirable to provide a solution that can reduce the increase in the array device threshold voltage. Exemplary embodiments of the invention actively adjust the substrate well voltage during operation of the memory device. This can reduce the body effect (i.e., variation of the threshold voltage due to a variation of the substrate or bulk voltage) and can therefore provide improved array device performance (e.g., reduced data corruption) while the word line (“WL”) is activated.